John Hauser

Berkeley HardFloat

Berkeley HardFloat is a free, high-quality Verilog encoding of digital hardware modules for binary floating-point arithmetic. HardFloat fully conforms to the IEEE Standard for Floating-Point Arithmetic, supporting all required rounding modes, exception flags, and special values, including subnormals. These operations are implemented:

A wide range of floating-point sizes is supported, with modules taking parameters that independently determine the widths of the exponent and significand fields. The set of possible formats includes the standard IEEE ones of 16-bit half-precision, 32-bit single-precision, 64-bit double-precision, and 128-bit quadruple-precision. For greater flexibility, HardFloat permits an operation’s rounding stage to be separated from its pre-rounding computation, allowing, for example, a single rounding stage to be shared by multiple functions, or an operation to be rounded to alternate result sizes (by instantiating multiple, different-sized rounding stages).

HardFloat converts IEEE-format floating-point inputs into a more convenient recoded format for its arithmetic operations. However, the results computed by HardFloat modules are always the exact values dictated by the IEEE Standard, just represented in the recoded format. Computed results can be converted back to a standard IEEE format at any time.

HardFloat is written for the 2001 standard for Verilog. Different floating-point specializations are provided to customize the arithmetic appropriately for Intel x86, Arm, or RISC-V processors. Other specializations can be crafted using these as examples.

Release 1

Berkeley HardFloat is currently in its inaugural release, Release 1 (2019 July). More information about this release is in the following files from the HardFloat package:
-- HardFloat-Verilog.html - Berkeley HardFloat Release 1: Verilog Modules.
-- HardFloat-test-Verilog.html - Berkeley HardFloat Release 1: Testing Using Verilog Simulation.
-- HardFloat-test-Verilator.html - Berkeley HardFloat Release 1: Testing Using Verilator.

The following archive contains all source code and documentation for Release 1:
-> zip archive,

Testing HardFloat in simulation

The HardFloat package includes testbenches that require either a Verilog simulator or Verilator. A Verilog simulator that may be used is Icarus Verilog:
[] Icarus Verilog is a free Verilog simulator supporting the 2005 Verilog Standard.
However, much faster simulation can be obtained using Verilator:
[] Verilator is a free tool that converts a subset of Verilog or SystemVerilog into equivalent C++ code.

HardFloat’s simulation testbenches depend on the testfloat_gen program from Berkeley TestFloat. TestFloat in turn depends on Berkeley SoftFloat. To perform these tests, the SoftFloat and TestFloat packages must be obtained and built separately:
[] Berkeley SoftFloat is a free software implementation of binary floating-point that conforms to the IEEE Standard for Floating-Point Arithmetic.
[] Berkeley TestFloat is a small collection of programs for testing that an implementation of binary floating-point conforms to the IEEE Standard for Floating-Point Arithmetic.

Credit and contacts

Berkeley HardFloat was written by me, John R. Hauser. Funding for the development of HardFloat was provided indirectly by portions of grants to the University of California, Berkeley, from Microsoft, Intel, DARPA, Nokia, NVIDIA, Oracle, Samsung, Google, Futurewei, Seagate, Siemens, and SK Hynix, and by a portion of a U.C. Discovery Grant. The HardFloat documentation has more details.

Bugs in HardFloat and other comments can be reported to me at

John Hauser, 2019 July 29