Ph.D. thesis by
John Reid Hauser,
University of California, Berkeley
As VLSI technology continues to improve, configurable hardware devices such as
PLDs are progressively replacing many specialized digital integrated circuits.
Field-programmable gate arrays (FPGAs) are one class of such devices,
characterized by their ability to be reconfigured as often as desired.
Lately, FPGAs have advanced to the stage where they can host large
computational circuits, giving rise to the study of reconfigurable
computing as a potential alternative to traditional microprocessors.
Most previous reconfigurable computers, however, have been ad hoc designs that
are not fully compatible with existing general-purpose computing paradigms.
This thesis examines the problem of combining reconfigurable hardware with a conventional processor into a single-chip device that can serve as the core of a general-purpose computer. The impact of memory cache stalls, of multitasking context switches, and of virtual memory page faults on the design of the reconfigurable hardware is considered. A possible architecture for the device is defined in detail and its implementation in VLSI studied. With basic development tools and a full-fledged simulator, several benchmarks are tested on the proposed architecture and their performance compared favorably against an existing Sun UltraSPARC. Some additional experiences with the architecture are also related, followed by suggestions for future research.
Adobe PDF document,
In two places, I wrote the word combinatorial instead of the intended word combinational (“combinational circuits”, “combinational calculation”).