John Hauser

“The SFRA: A Corner-Turn FPGA Architecture”

Article by Nicholas Weaver, John Hauser, and John Wawrzynek, published in Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field-Programmable Gate Arrays (FPGA ’04, February 22–24, 2004), pp. 3–12.
10 pages.

Abstract: FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. When FPGAs are used as computational devices in a larger system, however, it is better to employ fixed-frequency FPGAs operating at a high clock frequency. Such fixed-frequency arrays require pipelined interconnect structures, which are difficult to support in a traditional FPGA architecture. We have developed a novel approach, called a “corner-turn” interconnect, based on a Manhattan array of logically depopulated S-boxes with full connectivity but limited routability. This interconnect supports new polynomial-time routing techniques while maintaining conventional placement and other upstream toolflow. We have used the corner-turn interconnect to define a fixed-frequency FPGA architecture, the SFRA, that is largely compatible with the Xilinx Virtex while providing higher speed, pipelined operation. Our tools automatically repipeline designs to operate at the SFRA’s intrinsic clock frequency. Since the arrays are largely compatible, we directly compare the SFRA with the Virtex on four benchmark designs. On these benchmarks, the SFRA offers higher throughput and competitive throughput per area. The SFRA routing and retiming tools also run one to two orders of magnitude faster than their Xilinx counterparts.

-> Adobe PDF document, 2004_Weaver_SFRA.pdf [203 kB].

John Hauser, 2017 November 2